Modeling of 7 Nano Meter Fin Field Effect Transistor for Evaluation of Fringe & Oxide Capacitance

Abstract

Fin-FET are insusceptible to short channel effects punch through, threshold voltage, leakage current but their concerts at high frequencies are conceded due to durable fringing field between gate and source with drain area. Because of high-technology progression, the gate construction of MOSFET has been upgraded from planar to nonplanar with an enrichment in the number of monitoring gates multiple gates on 3 sides. In this paper we mention Fin-FET assembly for high frequency applications.

MOS-FET plays very energetic role but scaling of device affected on performance parameters like speed and power. Fin-FET is non planar novel device to solve the short channel effects which occurs due to scaling. Non-planar structure of Fin-FET parasitic capacitances like gate oxide overlap and fringe capacitance makes adverse effect like lower switching speed of device, making result on delay ion and ioff of device. In this paper we planned Fin-FET design procedure to measure oxide and fringe capacitance with low k dielectric spacer thickness and increase ion to recover device driving ability. Effect on threshold voltage having observed with low k spacer at least count of 0.051 V.  By using 4.65 eV metal gate work function with front, top and back gate we control leakage current and threshold voltage. Seven nano meter gate length Fin-FET is design We measured oxide capacitance of 0.464 F for 19.28 GHz and fringe capacitance (69.66 nf) for 4.88 GHz frequency by designing the Fin-FET with high-K SOI MOSFETs which support 11.4 nA leakage current to improve the speed of the processor.

In this research work, design topologies of Single Finger Fin Filed Effect Transistors are discussed and evaluate the probable result of fringe and parasitic capacitance from fringing area on the device. By using geometry of device like fin width, height, thickness and multiple fingers we measure the fringe capacitance and oxide capacitance of designed Fin-FET.

HIGHLIGHTS

• In this Paper, we focus on fundamentals of novel device Fin-FET its working construction & design based on geometry parameter & capacitance measurement by designing model of 7 nm gate length
• In this work, we focus on how Fin-FET helps to reduce short channel effect by possessions of geometry parameters like gate length and Fin thickness & progress the performance of the nanoscale device
• From the simulation results we observe lowering of drain induced barrier lowering, subthreshold slope and leakage current, whereas threshold voltages rise
• From the observation, SCE has been attributed to the distribution of the junction electric fields into the channel region, producing lower DIBL which decreases V_TH

GRAPHICAL ABSTRACT